Review Paper on Reduced Power Consumption using Flip Flop
نویسندگان
چکیده
منابع مشابه
Power Consumption and BER of Flip-Flop Inserted Global Interconnect
In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication—a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth ...
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ژورنال
عنوان ژورنال: International Journal of Electronics and Communication Engineering
سال: 2016
ISSN: 2348-8549
DOI: 10.14445/23488549/ijece-v3i5p112